Firmwares for high-speed signal processing applications

Matrix-vector multiplication is widely used in science and engineering. With the constant increase in data throughput rates, computing matrix operations of large sizes efficiently is becoming increasingly important. Thus, this project looks at designing specialised hardware to compute matrix-vector multiplications with more speed and efficiency. The design takes advantage of previous architecture designs with the aim of creating an efficient pipelined and parallelised system that can be dropped into any external hardware interface. The design was implemented using Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) and simulated on both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) technologies. Results gained have in many cases improved on previous designs, with some suggestions given on further future architecture improvements.