Dead-time compensation for multilevel cascaded H-bridge converters with novel voltage balancing
conference contribution
posted on 2025-05-09, 05:59 authored by R. E. Betz, Terrence SummersTerrence Summers, Galina MirzaevaGalina MirzaevaA novel capacitor voltage balancing algorithm for cascaded H-bridge converters can lead to undesirable voltage spikes at the output of the converter. This paper describes the voltage balancing algorithm and how it produces the voltage spikes. A simple and elegant solution is then developed and simulation results are presented to demonstrate its performance.
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Source title
Proceedings of EPE '09: 13th European Conference on Power Electronics and ApplicationsName of conference
13th European Conference on Power Electronics and Applications (EPE '09)Location
Barcelona, SpainStart date
2009-09-08End date
2009-09-10Publisher
Institute of Electrical and Electronics Engineers (IEEE)Place published
Piscataway, NJLanguage
- en, English
College/Research Centre
Faculty of Engineering and Built EnvironmentSchool
School of Electrical Engineering and Computer ScienceRights statement
Copyright © 2009 IEEE. Reprinted from the Proceedings of EPE '09: 13th European Conference on Power Electronics and Applications. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of University of Newcastle's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.Usage metrics
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